1. Field of the Invention
The invention relates to an apparatus and method of bridging two PCI buses together, and more particularly to a PCI-to-PCI repeater.
2. Description of the Related Art
The performance of a personal computer (PC) is dependent upon many factors, such as the speed of the processor, memory and input/output (I/O) subsystem. With the introduction of the peripheral component interconnect (PCI) bus in 1992, the I/O subsystem was given a high performance bus from which to operate.
Originally, the PCI bus was not intended to supplant the existing expansion buses, such as the industry standard architecture (ISA) bus or extended industry standard architecture (EISA). However, pressure from the computer industry and competing buses caused the PCI bus to be available for expansion bus purposes. Thus, computer systems may incorporate PCI devices onto the motherboard or provide support for add-in boards.
The PCI bus is referred to as a mezzanine bus, or a local bus, because it usually resides between the very high performance processor bus and the lower performance ISA or EISA bus. The logic that connects one computer bus to another, allowing an agent on one bus to access an agent on the other, is known as a bridge. In PCI vernacular, an agent is any entity or device that operates on a computer bus. An agent can be either a bus master or bus slave. Bus masters, or initiators, initiate bus transactions and bus slaves, or targets, respond to a bus transaction initiated by a bus master. Oftentimes, an initiator is on one bus and the target is on another.
The bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address space of the computer system. The primary function of a bridge is to map the address space of one bus into the address space of another bus. The PCI bus defines three physical address spaces: memory, I/O space, and configuration space. Address decoding on the PCI bus is distributed; i.e. each device coupled to the PCI bus performs address decoding. The PCI specification defines two styles of address decoding: positive and subtractive. Positive decoding is faster since each PCI device is looking for accesses in the address range(s) the device has been assigned. Subtractive decoding can be implemented by only one device on the PCI bus since the subtractive decoding device accepts all accesses not positively decoded by some other agent.
Every PCI transfer begins with an address phase, during which an address/data bus (AD31:0!) transfers the address and a command/byte enable (C/BE.sub.-- 3:0!) bus transfers a command code. One or more data phases follows this phase, during which the same address/data bus transfers data and the command/byte enable bus transfers byte-enable signals. In a burst cycle, multiple data phases can follow a single address phase. In PCI terminology, the requesting PCI device is known as the initiator, and the addressed PCI device as the target. Every transfer starts with the activation of the frame (FRAME.sub.--) signal.
A device selection (DEVSEL#) signal is driven by the target to indicate that it is responding to the transaction. A device decodes the address/data lines and asserts a device select (DEVSEL#) signal if it owns the starting address. DEVSEL# may be driven with slow, medium or fast timing. If no agent asserts DEVSEL# within the slow timing parameters, the agent performing subtractive decoding may claim and assert DEVSEL#. The "#" or ".sub.-- " refers to active low signals. More details on the PCI bus and particularly PCI addressing are found in the PCI Local Bus Specification, Production Version, Revision 2.1, dated Jun. 1, 1995, which is published by the PCI Special Interest Group of Hillsboro, Oreg. and hereby incorporated by reference.
The target indicates its readiness with an active target ready (TRDY.sub.--) signal. An active TRDY.sub.-- during a write access indicates that the target can take the data from the address/data bus. An active TRDY.sub.-- during a read access indicates that the requested data is available on the address/data bus.
In addition, the initiator must also indicate its readiness to the PCI bridge, through an active initiator ready (IRDY.sub.--) signal. An active IRDY.sub.-- during a write access indicates that the initiator has sent the write data on the address/data bus. In a read access, an active IRDY.sub.-- indicates that it accepts the data from the address/data bus. The initiator ends or interrupts the transfer by deactivating the FRAME.sub.-- signal. The target can also stop the transfer by activation of a stop (STOP.sub.--) signal.
As defined, the PCI bus is limited to ten loads. A PCI device incorporated onto the motherboard is essentially one load and a PCI slot is considered two loads. Hence, a computer system with a processor/PCI bridge, three PCI slots and a PCI/ISA bridge is limited to two motherboard devices. Since oftentimes two motherboard devices is too limiting, it is desirable to exceed the ten load limit.
One method of extending the number of loads described in the above-referenced PCI Specification is to use multiple PCI buses. Multiple PCI buses provide support for more devices than can be directly connected to one PCI bus. There are two ways to organize multiple PCI buses: as peers of each other or hierarchically. Peer buses require multiple bridges on the processor bus that may affect loading. A hierarchical configuration has advantages if I/O patterns tend to be from one PCI device to another. If most I/O traffic goes into and out of memory, then peer buses make more sense. However, either bus configuration requires that the bridges be configured at startup to respond to an access on their primary bus only if the address falls into a specified range. Furthermore, bridges separate the bus into two logical buses, thereby further complicating the configuration.
Each bridge includes address registers that are programmable through configuration space, so that the bridge responds to an access on its primary bus only if the address falls into the range specified by those registers; otherwise the access is claimed by a subtractive decode agent. Only one set of address range response registers is required by the PCI. Specification; however, if multiple buses are provided, the complexity of the address may increase and multiple sets of registers are needed. Generally, the address range response registers are programmed to correspond to the addresses unused by the primary bus, instead of the memory space required by the secondary bus. Thus, the secondary side of the bridge responds to all memory accesses except those that fall into the ranges specified by the address response range registers. All transactions initiated on the secondary bus, outside of the programmed range, are responded to on the primary bus. It is the responsibility of system software to maintain the address response range registers of the bridges so that address decoding is properly performed.
The configuration of the address range register grows even more complicated if devices are allowed to be hot-pluggable. Hot pluggable devices, such as PC Cardbus cards, cause problems since the address range changes with the insertion or removal of the hot pluggable device. Therefore, it is desirable to remove this level of complexity and simultaneously provide a high number of PCI loads for sufficient functionality and expandability.
Transparent bridges have attempted to solve the configuration problem by making the bridge appear invisible to software. However, the performance of such bridges is often less than desirable. Cycles that were performed on the primary bus at top PCI bus speed take three times as long to complete on the secondary bus, if proper PCI timing conventions are followed. Therefore, a higher performing transparent bridge is desirable.